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AD1836A Arkusz danych(PDF) 20 Page - Analog Devices

Numer części AD1836A
Szczegółowy opis  Multichannel 96 kHz Codec
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Strona internetowa  http://www.analog.com
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AD1836A Arkusz danych(HTML) 20 Page - Analog Devices

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AD1836A
Table 15. DAC Control Register 2
DAC Mute
Address
RD/WR
Reserved
DAC3R
DAC3L
DAC2R
DAC2L
DAC1R
DAC1L
15, 14, 13, 12
11
10, 9, 8, 7, 6
5
4
3
2
1
0
0001
0
00000
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
Table 16. DAC Volume Registers
Function
Address
RD/WR
Reserved
Volume
15, 14, 13, 12
11
10
9:0
0010: DAC1L
0011: DAC1R
0100: DAC2L
0101: DAC2R
0110: DAC3L
0111: DAC3R
0
0
0 to 1023 in 1024 Linear Steps
Table 17. ADC Control Register 1
Function
Address
RD/WR
Reserved
Filter
Power-Down
Sample Rate
Left Gain
Right Gain
15, 14, 13, 12
11
10, 9
8
7
6
5, 4, 3
2, 1, 0
1100
0
00
0 = DC
1 = High Pass
0 = Normal
1 = PWRDWN
0 = 48 kHz
1 = 96 kHz
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Reserved
110 = Reserved
111 = Reserved
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Reserved
110 = Reserved
111 = Reserved
Table 18. ADC Control Register 2
Packed Mode: Eight channels are “packed” in ASDATA1 serial output. Packed Mode 128: Refer to Figure 5. Packed Mode 256: Refer to Figure 6.
Packed Mode AUX: Refer to Figure 9 to Figure 11. Note that Packed AUX mode affects the entire chip, including the DAC serial mode.
ADC Mute
Address
RD/WR
Reserved
Master/Slave
AUX Mode
SOUT Mode
Word Width
ADC2R
ADC2L
ADC1R
ADC1L
15, 14, 13, 12
11
10
9
8, 7, 6
5, 4
3
2
1
0
1101
0
0
0 = Slave
1 = Master
000 = I2S
001 = RJ
010 = DSP
011 = LJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Packed Mode AUX
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
Rev. 0 | Page 20 of 24


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