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DAC8812C Arkusz danych(PDF) 5 Page - Texas Instruments |
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DAC8812C Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 18 page www.ti.com PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 DGND DAC8812 (TOP VIEW) AGNDA IOUTA VREFA RFBA RFBB VREFB IOUTB AGNDB LDAC MSB RS VDD CS CLK SDI DAC8812 SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005 PIN DESCRIPTION PIN NAME DESCRIPTION 1 RFBA Establish voltage output for DAC A by connecting to external amplifier output. DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage. Can 2 VREFA be tied to VDD pin. 3 IOUTA DAC A Current output. 4 AGNDA DAC A Analog ground. 5 AGNDB DAC B Analog ground. 6 IOUTB DAC B Current output. DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage. Can 7 VREFB be tied to VDD pin. 8 RFBB Establish voltage output for DAC B by connecting to external amplifier output. 9 SDI Serial data input; data loads directly into the shift register. Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale. 10 RS Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812. Chip-select; active low input. Disables shift register loading when high. Transfers serial 11 CS register data to input register when CS goes high. Does not affect LDAC operation. 12 DGND Digital ground. 13 VDD Positive power-supply input. Specified range of operation 2.7 V to 5.5 V. MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system 14 MSB power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or VDD. Load DAC register strobe; level sensitive active low. Transfers all input register data to the 15 LDAC DAC registers. Asynchronous active low input. See Table 2 for operation. 16 CLK Clock input. Positive edge clocks data into shift register. 5 |
Podobny numer części - DAC8812C |
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Podobny opis - DAC8812C |
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