AD5535 datasheet(11/16 Pages) AD

Numer części	AD5535

Szczegółowy opis	32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V

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Preliminary Technical Data

AD5535

Rev. PrE | Page 11 of 16

FUNCTIONAL DESCRIPTION

The AD5535 consists of 32 14-bit DACs with 200 V high voltage

amplifiers in a single 15 mm × 15 mm CSP-BGA package. The

output voltage range is programmable via the REFIN pin.

Output range is 0 V to 50 V with REFIN = 1 V, and 0 V to 200 V

with REFIN = 4 V. Communication to the device is through a

serial interface operating at clock rates of up to 30 MHz and is

compatible with DSP and microcontroller interface standards. A

5-bit address and a 14-bit data-word are loaded into the

AD5535 input register via the serial interface. The channel

address is decoded, and the data-word is converted into an

analog output voltage for this channel.

At power-on, all the DAC registers are loaded with 0s.

DIGITAL-TO-ANALOG SECTION

The architecture of each DAC channel consists of a resistor

string DAC followed by an output buffer amplifier operating

with a nominal gain of 50. The voltage at the REF_IN pin

provides the reference voltage for the corresponding DAC. The

input coding to the DAC is straight binary and the ideal DAC

output voltage is given by

14

_

2

50

D

V

IN

REF

OUT

×

=

where D is the decimal equivalent of the binary code, which is

loaded to the DAC register (0 to 16,383).

The output buffer amplifier is specified to drive a load of 1 MΩ

and 200 pF. The linear output voltage range for the output

amplifier is from 7 V to VPP − 10V. The amplifier output band-

width is typically 5 kHz, and is capable of sourcing 700 µA and

sinking 2.8mA. Settling time for a full-scale step is typically

30 µs with no load and 110 µs with a 200 pF load.

RESET FUNCTION

The reset function on the AD5535 can be used to reset all nodes

on the device to their power-on reset condition. All the DACs

are loaded with 0s and all registers are cleared. The reset

function is implemented by taking the RESET pin low.

SERIAL INTERFACE

The serial interface is controlled by three pins:

• SYNC is the frame synchronization pin for the serial

interface.

• SCLK is the serial clock input. This pin operates at clock

speeds of up to 30 MHz.

• D

IN

is the serial data input. Data must be valid on the falling

edge of SCLK.

To update a single DAC channel, a 19-bit data-word is written

to the AD5535 input register.

A4 to A0 Bits

These bits can address any one of the 32 channels. A4 is the

MSB of the address; A0 is the LSB.

DB13 to DB0 Bits

These bits are used to write a 14-bit word into the addressed

DAC register.

Figure 2 is the timing diagram for a serial write to the AD5535.

The serial interface works with both a continuous and a discon-

tinuous serial clock. The first falling edge of SYNC resets a

counter that counts the number of serial clocks to ensure that

the correct number of bits are shifted into the serial shift

register. Any further edges on SYNC are ignored until the

correct number of bits are shifted in. Once 19 bits have been

shifted in, the SCLK is ignored. For another serial transfer to

take place, the counter must be reset by the falling edge of

SYNC. The user must allow 200 ns (minimum) between

successive writes.

A4

A3

A2

A1

A0

DB13–DB0

MSB

LSB

Figure 10. Serial Data Format

MICROPROCESSOR INTERFACING

AD5535 to ADSP-21xx Interface

The ADSP-21xx family of DSPs is easily interfaced to the

AD5535 without the need for extra logic. A data transfer is

initiated by writing a word to the TX register after the SPORT

has been enabled. In a write sequence, data is clocked out on

each rising edge of the DSP’s serial clock and clocked into the

AD5535 on the falling edge of its SCLK. The easiest way to

provide the 19-bit data-word required by the AD5535, is to

transmit two 10-bit data-words from the ADSP-21xx. Ensure

that the data is positioned correctly in the TX register so that

the first 19 bits transmitted contain valid data.

Set up the SPORT control register as follows:

TFSW = 1, Alternate Framing

INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = 1, Frame Every Word

ITFS = 1, Internal Framing Signal

SLEN = 1001, 10-Bit Data Word

Figure 11 shows the connection diagram.

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