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ADSP-TS201SABP-X Arkusz danych(PDF) 5 Page - Analog Devices |
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ADSP-TS201SABP-X Arkusz danych(HTML) 5 Page - Analog Devices |
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5 / 40 page  ADSP-TS201S Preliminary Technical Data Rev. PrH | Page 5 of 40 | December 2003 Because the IALU’s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hard- ware (register dependency check) causes a stall if a result is unavailable in a given cycle. PROGRAM SEQUENCER The ADSP-TS201S processor’s program sequencer supports the following: • A fully interruptible programming model with flexible pro- gramming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles • A ten-cycle instruction pipeline—four-cycle fetch pipe and six-cycle execution pipe—computation results available two cycles after operands are available • Supply of instruction fetch memory addresses; the sequencer’s Instruction Alignment Buffer (IAB) caches up to five fetched instruction lines waiting to execute; the pro- gram sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution • Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instruc- tions, loop structures, conditions, interrupts, and software exceptions • Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches that are taken occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty • Compact code without the requirement to align code in memory; the IAB handles alignment Interrupt Controller The DSP supports nested and nonnested interrupts. Each inter- rupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level-sensitive or edge-sensitive, except the IRQ3–0 hardware interrupts, which are programmable. The DSP distinguishes between hardware interrupts and soft- ware exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe. Flexible Instruction Set The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the DSP to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include: • CLU instructions for communications infrastructure to govern Trellis Decoding (for example, Viterbi and Turbo decoders) and Despreading via complex correlations • Algebraic assembly language syntax • Direct support for all DSP, imaging, and video arithmetic types • Eliminates toggling DSP hardware modes because modes are supported as options (for example, rounding, satura- tion, and others) within instructions • Branch prediction encoded in instruction; enables zero- overhead loops • Parallelism encoded in instruction line • Conditional execution optional for all instructions • User defined partitioning between program and data memory DSP MEMORY The DSP’s internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 3. The memory map is divided into four memory areas—host space, external memory, multiprocessor space, and internal memory—and each memory space, except host memory, is sub- divided into smaller memory spaces. The ADSP-TS201S processor internal memory has 24M bits of on-chip DRAM memory, divided into six blocks of 4M bits (128K words × 32 bits). Each block—M0, M2, M4, M6, M8, and M10—can store program, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the DSP to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single cycle accesses to internal DRAM. The six internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the DSP to perform four memory transfers in the same cycle. The DSP’s internal bus architecture provides a total memory bandwidth of 33.6G bytes per second, enabling the core and I/O to access eight 32-bit data words and four 32-bit instructions each cycle. The DSP’s flexible memory structure enables: • DSP core and I/O accesses to different memory blocks in the same cycle • DSP core access to three memory blocks in parallel—one instruction and two data accesses • Programmable partitioning of program and data memory • Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB |
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