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TPPM0110DWP Arkusz danych(PDF) 10 Page - Texas Instruments |
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TPPM0110DWP Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 14 page TPPM0110 DUAL LOW-DROPOUT LINEAR REGULATOR SLVS365 –MARCH 2001 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION packaging To maximize the efficiency of this package for application on a single layer or multilayer PCB, certain guidelines must be followed. The following information is to be used as a guideline only. For further information, refer to the PowerPAD concept implementation document. multilayer PCB The following are guidelines for mounting the PowerPAD IC on a multilayer PCB with a ground plane. Solid Pad (Land Pattern) Package Thermal Pad Thermal Vias Via = 0,33 mm Diameter Minimum Pitch Between Vias is 1,52 mm Package Outline Figure 8. Package and Land Configuration for a Multilayer PCB 4 Plane 0,18 mm (Square) Package Solder Pad Component Traces Thermal Via Thermal Isolation Power Plane Only Package Solder Pad (Bottom Trace) 2 Plane 1,5038 – 1,5748 mm Component Trace (2 oz Cu) 1,0142 – 1,0502 mm Ground Plane (1 oz Cu) 0,5246 – 0,5606 mm Power Plane (1 oz Cu) 0 – 0,071 mm Board Base and Bottom Pad 1,5748 mm Figure 9. Multilayer Board (Side View) |
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