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TSC51C2XXX16IBB Arkusz danych(PDF) 8 Page - TEMIC Semiconductors |
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TSC51C2XXX16IBB Arkusz danych(HTML) 8 Page - TEMIC Semiconductors |
8 / 28 page TSC8051C2 Rev. A (10 Jan. 97) 8 Preview MATRA MHS OUTPUT FUNCTION READ INTERNAL READ LATCH PORT 0 BIT TO LE Q WRITE LATCH MUX LATCH WRITE LATCH WRITE TO WRITE TO LATCH TO LATCH READ LATCH MUX PORT 1 BIT DQ P0.X P0.X PIN VCC CONTROL ADDR/DATA INT. BUS PIN READ LATCH DQ P1.X LATCH LE Q P1.X PIN VCC CONTROL PWMX INT. BUS READ PIN PULL–UP* DQ P2.X LE Q P2.X PIN VCC CONTROL ADDR INT. BUS READ PIN INTERNAL PULL–UP READ LATCH DQ P3.X LATCH LE Q P3.X PIN VCC INT. BUS ALTERNATE ALTERNATE INPUT FUNCTION READ PIN INTERNAL PULL–UP LATCH PORT 2 BIT PORT 3 BIT MUX * Internal pull–up not present on P1.0 to P1.4 when PWM8 to PWM11 and CPO are enabled Figure 4. Port Bit Latches and I/O buffers 6.5. Reset Circuitry The reset circuitry for the TSC8051C2 is connected to the reset pin RST. A Schmitt trigger is used at the input for noise rejection (see Figure 5. ). A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. It also configures the ALE and PSEN pins as inputs (they are quasi–bidirectional). A Watchdog timer underflow or a power Fail condition if enabled, will force a reset condition to the TSC8051C2 by an internal connection. The internal reset is executed during the second cycle in which reset is high and is repeated every cycle until RST goes low. It leaves the internal registers as follows: Register Content ACC 00h B 00h DPTR 0000h EICON 00h HWDR 00h IE 0XX0 0000b IP XXX0 0000b MSCON XXXX XXX0b MXCR0–1 00h P0–P3 FFh PC 0000h PCON 0XX0 0000b PSW 00h PWM0–11 00h PWMCON XXXX XXX0b SBUF 00h |
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