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ADS5433 Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS5433 Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 22 page  www.ti.com TIMING REQUIREMENTS (1) N N+1 N+2 N+3 N+4 N N−1 N−2 N−3 tA tsu(C) th(C) th(DR) N + 1 N N + 2 N + 3 N + 4 tC_DR tr tCLK tCLKL CLK, CLK D[13:0], OVR DRY AIN tCLKH tDR tsu(DR) tf T0073-02 ADS5433 SLAS503 – APRIL 2006 Over full temperature range, AV DD = 5 V, DRVDD = 3.3 V, sampling rate = 80 MSPS PARAMETER MIN TYP MAX UNIT APERTURE TIME tA Aperture delay 500 ps tJ Clock slope independent aperture uncertainity (jitter) 150 fs kJ Clock slope dependent jitter factor 50 µV CLOCK INPUT tCLK Clock period 12.5 ns tCLKH(2) Clock pulsewidth high 6.25 ns tCLKL(2) Clock pulsewidth low 6.25 ns CLOCK TO DATAREADY (DRY) tDR Clock rising 50% to DRY falling 50% 2.8 3.9 4.7 ns tC_DR Clock rising 50% to DRY rising 50% tDR + tCLKH ns tC_DR_50% Clock rising 50% to DRY rising 50% with 50% duty cycle clock 9 10.1 11 ns CLOCK TO DATA, OVR(4) tr Data VOL to data VOH (rise time) 2 ns tf Data VOH to data VOL (fall time) 2 ns L Latency 3 Cycles tsu(C) Valid DATA(3) to clock 50% with 50% duty cycle clock (setup time) 4.8(4) 6.3 ns tH(C) Clock 50% to invalid DATA(3) (hold time) 2.6 3.6 ns DATAREADY (DRY) to DATA, OVR(5) tsu(DR)_50% Valid DATA(3) to DRY 50% with 50% duty cycle clock (setup time) 3.3(6) 4 ns th(DR)_50% DRY 50% to invalid DATA(3) with 50% duty cycle clock (hold time) 5.4 5.9 ns (1) All values obtained from design and characterization. (2) See Figure 1 for more information. (3) See VOH and VOL levels. (4) tSU(C) = tCLK– tCLK(min) + tSU(C)(min), where tCLK(min) = 12.5 ns and tSU(C)(min) = 4.8 ns for all sample rates equal to or below 80MSPS. (5) Data is updated with clock rising edge or DRY falling edge. (6) tSU(DR)50% = (tCLK / 2) – (tCLK(min) / 2) + tSU(DR)(min), where tCLK(min) = 12.5 ns and tSU(DR)(min) = 3.3 ns for all sample rates equal to or below 80MSPS. Figure 1. Timing Diagram 6 Submit Documentation Feedback |
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