SN74AUCH16374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES404D – JULY 2002 – REVISED MAY 2003

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VCC/2

th

tsu

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

S1

2

× VCC

Open

GND

RL

RL

Data Input

Timing Input

VCC

0 V

VCC

0 V

0 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VCC

0 V

Input

Output

Waveform 1

S1 at 2

× VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VCC

0 V

VOL + V

∆

VOH – V

∆

≈0 V

VCC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2

× VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VCC

VCC/2

VCC/2

0.8 V

1.2 V

± 0.1 V

1.5 V

± 0.1 V

1.8 V

± 0.15 V

2.5 V

± 0.2 V

2 k

Ω

2 k

Ω

2 k

Ω

1 k

Ω

500

Ω

VCC

RL

0.1 V

0.1 V

0.1 V

0.15 V

0.15 V

V

∆

CL

15 pF

15 pF

15 pF

30 pF

30 pF

Figure 1. Load Circuit and Voltage Waveforms