MEMSIC MXC6202xJ/K Rev.A
Page 9 of 11
3/20/2006
on the SDA line has to be stable during the HIGH
period of the SCL line. In other words, valid data can
only change when the SCL line is LOW.
I
2C BUS DATA TRANSFER
A data transfer is started with a “START” condition
and ended with a “STOP” condition.
A “START”
condition is defined by a HIGH to LOW transition on
the SDA line while SCL line is HIGH.
A “STOP”
condition is defined by a LOW to HIGH transition on
the SDA line while SCL line is HIGH. All data transfer
in I
2C system is 8-bits long. Each byte has to be
followed by an acknowledge bit. Each data transfer
involves a total of 9 clock cycles. Data is transferred
starting with the most significant bit (MSB). After a
“START” condition, the master device calls a specific
slave device, in our case, the MEMSIC accelerometer
with a 7-bit device address.
To avoid potential
address
conflict,
either
by
ICs
from
other
manufacturers or by other MEMSIC accelerometers
on the same bus, a total of 8 different addresses can
be programmed into a MEMSIC device at the factory.
Following the 7-bit address, the 8
th bit determines the
direction of data transfer: [1] for READ and [0] for
WRITE. After being addressed, the available MEMSIC
device being called will respond by an “Acknowledge”
signal, which is pulling SDA line LOW.
In order to read an acceleration signal, the master
device should operate a WRITE action with a code of
“[xxxxxxx0]” into the MEMSIC device 8-bit internal
register.
Bit
Name
Function
0
PD (Power Down)
Power down [1]/on [0]
1
Reserved
NC
2
BGTST (bandgap test)
Bandgap test [1]/normal[0]
3
TOEN
(temperature
out enable)
Temp Out EN [1]/disable[0]
BGTST is used to calibrate the temperature output
signal’s initial offset. By flipping the BGTST bit and
taking the average of two readings, the temperature
output initial offset will be calibrated to within
datasheet specifications.
After writing code of “[xxxxxxx0]” into the control
register, if a “READ” signal is received, during next 9
clock cycles, the MEMSIC device being called will
transfer 8-bits of data to the I
2C bus. If an
“Acknowledge” by master device is received, the
MEMSIC device will continue to transfer the next byte.
The same procedure repeats until 5 bytes of data are
transferred to master device. Those 5 bytes of data
are defined as following (“T” is temperature output):
1. Internal register
2. MSB X/T axis
3. LSB X/T axis
4. MSB Y axis
5. LSB Y axis
Even though each axis consists of two bytes, which
are 16-bits of data, the actual accelerometer
resolution is limited to 12bits. Unused MSB’s will be
simply filled by “0”s.
Note that the temperature output shares the same
registers with the X channel output. The implementer
can select which signal needs to be read out by using
the TOEN bit.
The master can stop slave data transfer after any of
the five bytes by not sending an acknowledge
command and followed by a “STOP” condition.
Data transfer
POWER DOWN MODE
The MEMSIC accelerometer can enter a power down
mode by the master device writing a code of
“[xxxxxxx1]” into the accelerometer’s internal register.
A wake up operation is performed when the master
writes into the same register a code of “[xxxxxxx0]”.
Note that it needs about 50mS (typical) for power up
time.
EXAMPLE OF DATA COMMUNICATION
First cycle: START followed by a calling to slave
address “[0010xxx]” to WRITE (8
th SCL, SDA keep
low). “[xxx]” Is determined by factory programming, a
total of 8 different addresses are available.
Second cycle: After an acknowledge signal is
received by the master device (MEMSIC device pulls
SDA line low during 9
th SCL pulse), the master device
sends “[00000000]” as the target address to be written
into. The MEMSIC device should acknowledge at the
end (9
th SCL pulse). Note: since the MEMSIC device
has only one internal register that can be written into,
user should always indicate “[00000000]” as the write
address.
Third cycle: Master device writes to internal MEMSIC
device memory code “[xxxxxxx0]” as a wake-up call.
The MEMSIC device should send an acknowledge
signal. A STOP command indicates the end of write
operation. A 100mS (typical) wait period should be
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