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LM27213 Arkusz danych(PDF) 3 Page - National Semiconductor (TI) |
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LM27213 Arkusz danych(HTML) 3 Page - National Semiconductor (TI) |
3 / 22 page Pin Descriptions (TSSOP/LLP) Pin 1, CBOOT: Connection for the high-side drive bootstrap capacitor. Pin 2, HG: High-side FET gate drive output. Pin 3, SW: Connect to switch node (drain of bottom power FET) to detect inductor current reversal. Also serves as the return path for the high-side FET gate drive currents. Pin 4, NC:No connect. Pin 5, SRCK: Source Kelvin. Connect directly to source of low-side FET to detect negative inductor current. Pin 6, NC: No connect Pin 7, ILIM: Over-current sense. Voltage between this pin and the regulator output is the voltage across the current sense resistor. Pin 8, ILIMREF: Current limit reference. Voltage between this pin and the regulator output sets the inductor current limit level. Pin 9, CMP: Current sense. Voltage between this pin and the regulator output sets the cycle by cycle inductor current. Pin 10, CMPREF: Inductor current reference. Voltage be- tween this pin and the regulator output programs the induc- tor current. Pin 11, VREF: Desired regulator output voltage under no load. Pin 12, CLK_EN#: Signal to start clock chip PLL locking. A low level indicates that the core supply is now stable and the CPU can begin clocking. Pin 13, DGND: Digital ground. Pin 14, PGOOD: Power good flag. Open-drain output. Logic high when output voltage enters the power good window and XPOK is asserted. Masked during transitions. Pin 15, XPOK: Input that tells the LM27213 that the supply voltage for the Memory Controller Hub is up. The LM27213 will regulate the output voltage to VBOOT until XPOK tran- sitions to a high state. PGOOD is forced low as long as this pin is low. Pin 16, SENSE: Regulator output voltage sense. Connect directly to output. Pin 17, VOVP: Over-voltage protection level. Connect this pin to the desired reference voltage to set the trigger level for over-voltage protection. Pins 18 P_Z2: Factory reference trim, do not connect. This pin must float. Pin 19, P_Z1: Factory reference trim, do not connect. This pin must float. Pins 20 NC: No connect. Pin 21, NC: No connect Pin 22, P_Z0: Factory reference trim, do not connect. This pin must float. Pin 23, SGND: Signal Ground. Pin 24, VDD: Chip power supply. Pin 25, SS: : Soft start, soft shutdown and slew rate control. Connect a capacitor between this pin and ground to control the soft start and soft shutdown speed. The value of the capacitor will also define the slew rate of the dynamic VID transitions. Pin 26, VIR7: 1.7V reference voltage. Pin 27, VBOOT: Initial output voltage desired after soft start completes. Connect this pin to the desired reference level. Pin 28, VSLP: Desired Voltage in Sleep Mode. Connect this pin to the desired reference level. Pin 29, NC: : No connect. Pin 30, NC: No connect. Pin 31, VDAC: Buffered Digital-to-Analog converter output. Pins 32, VSTP: Desired output voltage in Stop CPU mode. Connect this pin to the desired reference level. Pin 33, SLP: When this pin is logic high, VREF voltage is equal to that on the VSLP pin. Pin 34, STP_CPU#: When this pin is logic low, VREF volt- age is equal to that on the VSTP pin. Pin 35, DE_EN#: Power saving mode trigger signal. En- ables diode emulation. Pin 36, VID5: 6th and most significant bit to program the output voltage. Pin 37, VID4: 5th bit to program the output voltage. Pin 38, VID3: 4th bit to program the output voltage. Pin 39, VID2: 3rd bit to program the output voltage. Pin 40, VID1: 2nd bit to program the output voltage. Pin 41, VID0: First and least significant bit to program the output voltage. Pin 42, VR_ON: Chip enable input. Pin 43, NC: No connect Pin 44, NC: No connect. Pin 45, PGND: Power Ground. Connect to ground plane. Pin 46, NC: Power ground connection. Pin 47, LG: Low-side FET gate drive output. Pin 48, PVDD: Power input for the gate drives. www.national.com 3 |
Podobny numer części - LM27213 |
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Podobny opis - LM27213 |
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