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SI8250-IM Arkusz danych(PDF) 7 Page - Silicon Laboratories |
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SI8250-IM Arkusz danych(HTML) 7 Page - Silicon Laboratories |
7 / 30 page Si8250/1/2 Preliminary Rev. 0.8 7 Table 5. ADC1 Specifications TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified. Parameter Conditions Min Typ Max Units Sampling Frequency ADCSP = 0 — 10 — Msps ADCSP = 1 — 5 — Resolution — — 6 Bits LSB Size 4 — 20 mV Differential Input Voltage Range Note 1 –32 — +31 LSB Common-mode input voltage range 0.8 — 1.3 V Integral Nonlinearity –2 — +2 LSB Differential Nonlinearity –1 — +1 LSB Gain Error — 5 — % Offset Error — 3 — mV Input Bias Current — 5 — µA Standby Mode Supply Current disabled — 0.1 — µA Operating Mode Supply Current — — 3 mA Notes: 1. LSB size (mV) is programmable using the RES[3:0] bits in the ADC1CN register. Table 6. DSP Filter Engine Electrical Specifications TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified. Parameter Conditions Min Typ Max Units Resolution1 —— 9 Bits Dithering2 —— 6 Bits Standby Mode Supply Current disabled — 0.1 — µA Notes: 1. Internal word length = 22 bits. 2. Up to a total 15 bits of resolution when dithering is enabled. |
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