10 / 16 page
August 2000
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/16
Ver 1.0
PID 2958 08/00
SyncMOS Technologies Inc.
SM2958
Tm.II
External Data Memory Read Cycle
#PSEN
ALE
#RD
PORT 0
PORT 2
TYHLH
TLLDV
TLLYL
TRLRH
TAVLL
TLLAX
TRLAZ
TAVYL
TAVDV
P2.0 - P2.7 or A8 - A15 from DPH
TRHDZ
TRHDX
A0 - A7
from Ri or DPL
DATA IN
A0 - A7
from PCL
INSTRL
IN
A8 - A15 from PCH
TRLDV
Tm.III External Data Memory Write Cycle
#PSEN
ALE
#WR
PORT 0
PORT 2
TLHLL
TYHLH
TAVLL
TLLAX
TQVWX
TLLYL
TAVYL
TWLWH
TWHQX
TQVWH
A0-A7
From PCL
INSTRL
IN
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
A0-A7
from Ri or DPL
DATA OUT