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ES35P16-75CC2R Arkusz danych(PDF) 11 Page - Excel Semiconductor Inc. |
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ES35P16-75CC2R Arkusz danych(HTML) 11 Page - Excel Semiconductor Inc. |
11 / 35 page ES I ES I 11 Rev. 0E May 11 , 2006 ES25P16 Excel Semiconductor inc. ADVANCED INFORMATION 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Pro- gram (PP or PPP), Erase (SE, BE or PE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The Write Enable (WEL) bit is reset under the follow- ing conditions : - Power-up - WRDI instruction completion - WRSR instruction completion - PP instruction completion - SE instruction completion - BE instruction completion 0 1 2 3 4 5 6 7 Figure 4. Write Enable ( WREN ) Instruction Sequence SCK CS# SI SO Instruction High Impedance 0 1 2 3 4 5 6 7 Figure 5. Write Disable ( WRDI ) Instruction Sequence SCK CS# SI SO Instruction High Impedance |
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