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STAC9460 Arkusz danych(PDF) 11 Page - List of Unclassifed Manufacturers

Numer części STAC9460
Szczegółowy opis  Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
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STAC9460 Arkusz danych(HTML) 11 Page - List of Unclassifed Manufacturers

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2-9460-D1-1-0-0801
11
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
PRELIMINARY
INFORMATION
8/2 4 /0 1
6.2.
Single Line Format
The Single line data mode for the STAC9460 allows data all six channels to be input to the
chip on a single SDATA_IN line, SD1 (Pin 15) and output to all six analog outs (Pins 23-
28). The ADC data will be valid during the first 20 SCLK cycles following a D_LRCLK tran-
sition.
6.3.
I2C-Bus Interface
The I2C-Bus of the STAC9460 operates in compliance with the I2C-Bus Interface Specifi-
cation from Philips Semiconductor. The I2C-Bus for the STAC9460 does include an Auto-
Increment feature not identified by the Phillips specification. For Example, a typical write
would have the following format:
START....Chip Address (8 bits)....Register Address(8
bits)....Data(Register Address 8 bits)....Data (Register Address +1 8 bits)....Data (Register
Address +2 8 bits)....STOP. The addresses will increment through the end of the address
space or until a "STOP" condition (as per I2C spec) is received by the part. For detailed
information relating to the I2C, please reference the I2C-Bus Interface Specification from
Philips Semiconductor. Additional information for the Address Registers can be found in
section 7.1.12
Bits/Sample
SCLK Rate
Notes
20
128 Fs
6 inputs, 2 outputs, BRM only
Table 2. Single Line 20 Bit Data Mode, Data Valid on Rising Edge of SCLK
Figure 7. Single Line 20 Bit Data Mode Timing Diagram
Left Channel
Right Channel
LRCK
SCLK
SDIN 1/2/3
SDATA_OUT
-1
+1
-1
M
S
B
-1
+1
-1
+1
+1
-1
+1
-1
+1
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
L
S
B
L
S
B
L
S
B
L
S
B
L
S
B
L
S
B
Front
Front
Rear
Rear
Center
Bass
SCL
SDA
Stop
Start
Start
Stop
Repeated
t
buf
t
hdst
t
high
t
hdst
t
f
t
susp
t
r
t
sust
t
sud
t
hdd
t
low
Figure 8. I2C Timing Diagram


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