16
2-9460-D1-1-0-0801
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
PRELIMINARY
INFORMATION
8/2 4 /0 1
7.1.7.
General Purpose Register (0Dh)
The MSB (MD) selects between the MIC inputs and the DIFF inputs being routed to
the ADCs. Bit D6 (HPFD) disables the ADC pass filter capability. The ADC High
Pass FIlter Freeze, bit D4, maintains the high pass filter output’s current DC offset
7.1.8.
Audio Port Control (0Eh)
The I2S port is controlled via the bits contained in this register. Formatting is con-
trolled by the Audio Data Format bits, ADF4..ADF0 (bits D4 .. D0) of the register.
The audio formats available are standard I2S, Left Justified, Right Justified (16, 20,
or 24-Bit) and One Line.
HPFF
FUNCTION
0
ADC High Pass Filter Not-Frozen
1
ADC High Pass Filter Frozen
Table 12. Bit D4: HPFD
MD
FUNCTION
0
Differential Input Selected
1
Microphone Selected
Table 13. Bit D5 Microphone Differential Mux By-Pass Control
HPFD
FUNCTION
0
ADC High Pass Filter Enabled
1
ADC High Pass Filter Disabled
Table 14. Bit D6 ADC High Pass Filter Disable
ADF4 .. ADF0
D4..D0
AUDIO DATA FORMAT
00000
I2S
00001
Left Justified
00010
16 bit Right Justified
01010
20 bit Right Justified
10010
24 bit Right Justified
00011
One Line
*
All settings not shown are Reserved
Table 15. Audio Data Format Selection
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