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ADC14155EB Arkusz danych(PDF) 1 Page - National Semiconductor (TI) |
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ADC14155EB Arkusz danych(HTML) 1 Page - National Semiconductor (TI) |
1 / 19 page ADC14155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter General Description The ADC14155 is a high-performance CMOS analog-to- digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dy- namic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 974 mW of power at 155 MSPS. The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power- down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. For optimum performance, it is recommended to operate the ADC14155 with a differential clock input, which doubles the clock amplitude compared with single-ended clock opera- tion. Clock mode (differential versus single-ended) and out- put data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14155 is available in a 48-lead LLP package and operates over the industrial temperature range of −40˚C to +85˚C. Features n 1.1 GHz Full Power Bandwidth n Internal sample-and-hold circuit n Low power consumption n Internal precision 1.0V reference n Single-ended or Differential clock modes n Data Ready output clock n Clock Duty Cycle Stabilizer n Dual +3.3V and +1.8V supply operation (+/- 10%) n Power-down mode n Offset binary or 2’s complement output data format n 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch) Key Specifications n Resolution 14 Bits n Conversion Rate 155 MSPS n SNR (f IN = 70 MHz) 71.4 dBFS (typ) n SFDR (f IN = 70 MHz) 85.3 dBFS (typ) n ENOB (f IN = 70 MHz) 11.5 bits (typ) n Full Power Bandwidth 1.1 GHz (typ) n Power Consumption 974 mW (typ) Applications n High IF Sampling Receivers n Wireless Base Station Receivers n Power Amplifier Linearization n Multi-carrier, Multi-mode Receivers n Test and Measurement Equipment n Communications Instrumentation n Radar Systems PRELIMINARY May 2006 © 2006 National Semiconductor Corporation DS201790 www.national.com |
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