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GS8180DV18D Arkusz danych(PDF) 9 Page - GSI Technology |
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GS8180DV18D Arkusz danych(HTML) 9 Page - GSI Technology |
9 / 28 page GS8180DV18D-250/200/167/133/100 Rev: 2.04 4/2005 9/28 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance. Separate I/O Burst of 4 SigmaQuad SRAM Truth Table A R W Previous Operation Current Operation D D D D Q Q Q Q K ↑ (tn) K ↑ (tn) K ↑ (tn) K ↑ (tn-1) K ↑ (tn) K ↑ (tn+1) K ↑ (tn+1½) K ↑ (tn+2) K ↑ (tn+2½) K ↑ (tn+1) K ↑ (tn+1½) K ↑ (tn+2) K ↑ (tn+2½) X 1 1 Deselect Deselect X X — — Hi-Z Hi-Z — — X 1 X Write Deselect D2 D3 — — Hi-Z Hi-Z — — X X 1 Read Deselect X X — — Q2 Q3 — — V 1 0 Deselect Write D0 D1 D2 D3 Hi-Z Hi-Z — — V 0 X Deselect Read X X — — Q0 Q1 Q2 Q3 V X 0 Read Write D0 D1 D2 D3 Q2 Q3 — — V 0 X Write Read D2 D3 — — Q0 Q1 Q2 Q3 Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. “—” indicates that the input requirement or output state is determined by the next operation. 3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations. 4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre- ceded by a Read command. 6. Users should not clock in metastable addresses. |
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