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GS816272C-200I Arkusz danych(PDF) 11 Page - GSI Technology |
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GS816272C-200I Arkusz danych(HTML) 11 Page - GSI Technology |
11 / 31 page GS816272C Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.18 11/2005 11/31 © 1999, GSI Technology 50% tKC VSS – 2.0 V 50% VSS VIH Undershoot Measurement and Timing Overshoot Measurement and Timing 50% tKC VDD + 2.0 V 50% VDD VIL Capacitance oC, f = 1 MHZ, VDD Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. DQ VDDQ/2 50 Ω 30pF* Output Load 1 * Distributed Test Jig Capacitance (TA = 25 = 2.5 V) |
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