Philips Semiconductors

Product specification

74ABT841

10-bit bus interface latch (3-State)

4

1995 Sep 06

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

to +85

°C

UNIT

Min

Typ

Max

Min

Max

Input clamp voltage

–0.9

–1.2

–1.2

V

2.5

3.5

2.5

V

High-level output voltage

3.0

4.0

3.0

V

2.0

2.6

2.0

V

Low-level output voltage

0.42

0.55

0.55

V

Power-up output low

0.13

0.55

0.55

V

Input leakage

Control pins

±0.01

±1.0

±1.0

µA

current

Data pins

±5

±100

±100

µA

Power-off leakage current

±5.0

±100

±100

µA

Power-up/down 3–state

±5.0

±50

±50

µA

3-State output High current

5.0

50

50

µA

3-State output Low current

–5.0

–50

–50

µA

Output high leakage current

5.0

50

50

µA

–50

–100

–180

–50

–180

mA

0.5

250

250

µA

Quiescent supply current

25

38

38

mA

0.5

250

250

µA

∆I

Additional supply current per

05

15

15

A

Additional supply current per

0.5

1.5

1.5

mA

0.5

1.5

1.5

mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

transition time of up to 100

µsec is permitted.

AC CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

WAVEFORM

UNIT

Min

Typ

Max

Min

Max

Propagation delay

Dn to Qn

2

2.1

2.0

4.1

4.0

5.5

5.5

2.1

2.0

6.2

6.2

ns

Propagation delay

LE to Qn

1

2.1

2.8

4.1

4.6

5.9

6.2

2.1

2.8

6.5

6.7

ns

Output enable time

to High and Low level

4

5

1.0

2.2

3.0

4.1

4.5

5.6

1.0

2.2

5.3

6.3

ns

Output disable time

from High and Low level

4

5

2.7

2.8

4.7

4.6

6.2

6.1

2.7

2.8

7.1

6.5

ns