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ADSP-21062L Arkusz danych(PDF) 5 Page - Analog Devices |
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ADSP-21062L Arkusz danych(HTML) 5 Page - Analog Devices |
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5 / 48 page  ADSP-21062/ADSP-21062L –5– REV. B include interrupt generation upon completion of DMA trans- fers and DMA chaining for automatic linked DMA transfers. Serial Ports The ADSP-21062 features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at the full clock rate of the processor, providing each with a maxi- mum data rate of 40 Mbit/s. Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via DMA. Each of the serial ports offers TDM multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated. Multiprocessing The ADSP-21062 offers powerful features tailored to multi- processor DSP systems. The unified address space (see Figure 4) allows direct interprocessor accesses of each ADSP- 21062’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21062s and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maxi- mum throughput for interprocessor data transfer is 240 Mbytes/s over the link ports or external port. Broadcast writes allow simulta- neous transmission of data to all ADSP-21062s and can be used to implement reflective semaphores. Link Ports The ADSP-21062 features six 4-bit link ports that provide addi- tional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously, with a maximum data throughput of 240 Mbytes/s. Link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. Program Booting The internal memory of the ADSP-21062 can be booted at system power-up from either an 8-bit EPROM, a host proces- sor, or through one of the link ports. Selection of the boot source is controlled by the BMS (Boot Memory Select), EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit host processors can be used for booting. Off-Chip Memory and Peripherals Interface The ADSP-21062’s external port provides the processor’s inter- face to off-chip memory and peripherals. The 4-gigaword off- chip address space is included in the ADSP-21062’s unified address space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses and I/O data—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for sim- plified addressing of page-mode DRAM. The ADSP-21062 provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements. Host Processor Interface The ADSP-21062’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-21062’s exter- nal port and is memory-mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-21062’s external bus with the host bus request ( HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-21062, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands. DMA Controller The ADSP-21062’s on-chip DMA controller allows zero- overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21062’s internal memory and either external memory, external peripherals or a host processor. DMA transfers can also occur between the ADSP-21062’s internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32-, or 48-bit words is performed during DMA transfers. Ten channels of DMA are available on the ADSP-21062—two via the link ports, four via the serial ports, and four via the processor’s external port (for either host processor, other ADSP-21062s, memory or I/O transfers). Four additional link port DMA channels are shared with serial port 1 and the external port. Programs can be downloaded to the ADSP- 21062 using DMA transfers. Asynchronous off-chip peripher- als can control two DMA channels using DMA Request/ Grant lines ( DMAR1-2, DMAG1-2 ). Other DMA features |
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