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74ALVCH16843 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74ALVCH16843
Szczegółowy opis  18-bit bus-interface D-type latch 3-State
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
2
1998 Aug 04
853–2108 019833
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and GND pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
GND
VCC
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
VCC
2Q6
2Q7
GND
2Q8
2CLR
1D0
GND
1D1
1D2
VCC
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
VCC
2D6
2D7
GND
2D8
2LE
1PRE
1CLR
2OE
1LE
2PRE
SH00143
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nDn to nQn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.2
2.1
ns
tPHL/tPLH
Propagation delay
nLE to nQn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.3
2.0
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
17
3
pF
CPD
Power dissi ation ca acitance er buffer
VI = GND to VCC1
Clocked mode
Output enabled
Output disabled
19
9
F
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
DRAWING
NUMBER
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
–40
°C to +85°C
74ALVCH16843 DGG
ACH16843 DGG
SOT364-1


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