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74AVC16834DGG Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74AVC16834DGG
Szczegółowy opis  18-bit registered driver with inverted register enable 3-State
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AVC16834DGG Arkusz danych(HTML) 7 Page - NXP Semiconductors

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Philips Semiconductors
Preliminary specification
74AVC16834
18-bit registered driver with inverted register enable
(3-State)
1999 Jul 23
7
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
(Continued)
VM = 0.5 VCC
VX = VOL + 0.300 V
VY = VOH – 0.300 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE (Continued)
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
CP INPUT
Yn OUTPUT
VI
GND
VOH
VOL
tPHL
tPLH
tW
1/fMAX
SH00135
VM
VM
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
An
INPUT
LE
INPUT
tSU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
tSU
th
VI
GND
VI
GND
VM
VM
SH00166
VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 4. Data set-up and hold times for the An input to the
LE input
VI
GND
An INPUT
VI
GND
VOH
Yn OUTPUT
VOL
CP INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SH00136
VM
VM
VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
tPLZ
tPZL
VI
nOE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
tPHZ
VM
VM
VM
tPZH
VX
VY
SH00137
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 6. 3-state enable and disable times


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