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74F169 Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74F169 Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 12 page Philips Semiconductors Product specification 74F169 4-bit up/down binary synchronous counter 1996 Jan 05 3 LOGIC SYMBOL 9 3456 15 11 12 13 14 1 2 7 10 CP CEP CET PE D0 D1 D2 D3 Q0 Q1 Q2 Q3 TC U/D SF00786 VCC = Pin 16 GND = Pin 8 LOGIC SYMBOL (IEEE/IEC) M4 [DOWN] 9 1 10 7 2 [1] 3 4 5 6 1, 7D 14 13 12 11 M1 [LOAD] SF00787 M2 [COUNT] M3 [UP] CTR DIV 16 [2] [4] [8] 15 3, 5 CT=15 4, 5 CT=0 G5 G6 2, 3, 5, 6+/C7 2, 4, 5, 6– FUNCTIONAL DESCRIPTION The 74F169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is Low, the data on the D0 - D3 inputs enter the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be Low and PE must be High; the U/D input determines the direction of counting. The Terminal Count (TC) output is normally High and goes Low, provided that CET is Low, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1) Count Enable = CEP ⋅CET⋅PE 2) Up: TC = Q0⋅Q3⋅(U/D)⋅CET 3) Down: TC = Q0⋅Q1⋅Q2⋅Q3⋅(U/D)⋅CET MODE SELECT — FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE CP U/D CEP CET PE Dn Qn TC OPERATING MODE ↑ X X X l l L (1) Parallel load (Dn →Qn) ↑ X X X X X H (1) ↑ h l l h X Count Up (1) Count Up (increment) ↑ l l l h X Count Down (1) Count Down (decrement) ↑ X h X h X qn (1) Hold (do nothing) ↑ X X X h X qn H H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition (1) = The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL). |
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