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74HCT112D Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74HCT112D Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 15 page 1998 Jun 10 8 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) TEST CONDITIONS 74HCT UNIT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nCP to nQ 21 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nCP to nQ 23 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nRD to nQ, nQ 22 37 46 56 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nSD to nQ, nQ 18 32 40 48 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 8 20 24 ns 4.5 Fig.6 tW set or reset pulse width LOW 18 10 23 27 ns 4.5 Fig.7 trem removal time nRD to nCP 20 11 25 30 ns 4.5 Fig.7 trem removal time nSD to nCP 20 −8 25 30 ns 4.5 Fig.7 tsu set-up time nJ, nK to nCP 16 7 20 24 ns 4.5 Fig.6 th hold time nJ, nK to nCP 0 −7 0 0 ns 4.5 Fig.6 fmax maximum clock pulse frequency 30 64 24 20 MHz 4.5 Fig.6 |
Podobny numer części - 74HCT112D |
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Podobny opis - 74HCT112D |
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