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74HCT112D Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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74HCT112D Arkusz danych(HTML) 9 Page - NXP Semiconductors |
9 / 15 page 1998 Jun 10 9 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC WAVEFORMS Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. handbook, full pagewidth MBK218 VM (1) nCP INPUT nSD INPUT nRD INPUT nQ OUTPUT nQ OUTPUT VM (1) VM (1) VM (1) VM (1) tW trem trem tW tPHL tPLH tPLH tPHL Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse width and the nRD and nSD to nCP removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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Podobny opis - 74HCT112D |
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