Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

74HCT112DB Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74HCT112DB
Szczegółowy opis  Dual JK flip-flop with set and reset; negative-edge trigger
Download  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HCT112DB Arkusz danych(HTML) 2 Page - NXP Semiconductors

  74HCT112DB Datasheet HTML 1Page - NXP Semiconductors 74HCT112DB Datasheet HTML 2Page - NXP Semiconductors 74HCT112DB Datasheet HTML 3Page - NXP Semiconductors 74HCT112DB Datasheet HTML 4Page - NXP Semiconductors 74HCT112DB Datasheet HTML 5Page - NXP Semiconductors 74HCT112DB Datasheet HTML 6Page - NXP Semiconductors 74HCT112DB Datasheet HTML 7Page - NXP Semiconductors 74HCT112DB Datasheet HTML 8Page - NXP Semiconductors 74HCT112DB Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 15 page
background image
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
FEATURES
• Asynchronous set and reset
• Output capability: standard
• ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nSD) and reset (nRD) inputs.
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
nCP to nQ, nQ
1719ns
nSD to nQ, nQ
1515ns
nRD to nQ, nQ
1819ns
fmax
maximum clock frequency
66
70
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
27
30
pF


Podobny numer części - 74HCT112DB

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Nexperia B.V. All right...
74HCT112D NEXPERIA-74HCT112D Datasheet
267Kb / 16P
   Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 4 - 11 January 2021
More results

Podobny opis - 74HCT112DB

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Nexperia B.V. All right...
74HCT112 NEXPERIA-74HCT112 Datasheet
267Kb / 16P
   Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 4 - 11 January 2021
74HCT107-Q100 NEXPERIA-74HCT107-Q100 Datasheet
259Kb / 15P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 3 - 7 July 2021
logo
NXP Semiconductors
74HC73 NXP-74HC73 Datasheet
457Kb / 16P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 04-19 March 2008
74HC73 PHILIPS-74HC73 Datasheet
52Kb / 7P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 03-12 November 2004
74LV107 PHILIPS-74LV107 Datasheet
121Kb / 12P
   Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
logo
Nexperia B.V. All right...
74HC73-Q100 NEXPERIA-74HC73-Q100 Datasheet
221Kb / 12P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 1 - 4 December 2020
74HC73 NEXPERIA-74HC73 Datasheet
245Kb / 13P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 7 - 13 September 2021
74HCT107 NEXPERIA-74HCT107 Datasheet
259Kb / 15P
   Dual JK flip-flop with reset; negative-edge trigger
Rev. 6 - 7 July 2021
logo
NXP Semiconductors
74HC107 PHILIPS-74HC107 Datasheet
53Kb / 7P
   Dual JK flip-flop with reset; negative-edge trigger
December 1990
logo
Nexperia B.V. All right...
74HC107-Q100 NEXPERIA-74HC107-Q100 Datasheet
747Kb / 17P
   Dual JK flip-flop with reset; negative-edge trigger
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com