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74HCT138 Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74HCT138 Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 7 page September 1993 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Active LOW mutually exclusive outputs • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The “138” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ”138” is identical to the “238” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT propagation delay CL = 15 pF; VCC = 5 V tPHL/ tPLH An to Yn 12 17 ns tPHL/ tPLH E3 to Yn En to Yn 14 19 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 67 67 pF |
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