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74HCT163D Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74HCT163D Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 11 page December 1990 10 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74HC/HCT163 AC WAVEFORMS Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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