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74HCT163DB Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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74HCT163DB Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 11 page December 1990 11 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74HC/HCT163 Fig.11 Waveforms showing the MR set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the CEP and CET set-up and hold times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. APPLICATION INFORMATION The HC/HCT163 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset. Fig.13 Modulo-5 counter. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.14 Modulo-11 counter. |
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