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74HCT165DB Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74HCT165DB Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 10 page December 1990 10 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74HC/HCT165 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE). CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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