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74HCT166DB Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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74HCT166DB Arkusz danych(HTML) 9 Page - NXP Semiconductors |
9 / 10 page December 1990 9 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74HC/HCT166 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. The changing to output assumes internal Q6 opposite state from Q7. The number of clock pulses required between the tPLH and tPHL measurements can be determined from the function table. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3V. Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay and the master reset to clock (CP) removal time. The number of clock pulses required between the tPLH and tPHL measurements can be determined from the function table. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3V. |
Podobny numer części - 74HCT166DB |
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Podobny opis - 74HCT166DB |
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