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74HCT193N Arkusz danych(PDF) 10 Page - NXP Semiconductors

Numer części 74HCT193N
Szczegółowy opis  Presettable synchronous 4-bit binary up/down counter
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HCT193N Arkusz danych(HTML) 10 Page - NXP Semiconductors

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December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT193
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
−40 to +85 −40 to +125
min.
typ.
max.
min. max. min.
max.
tPHL/ tPLH
propagation delay
CPU,CPD to Qn
23
43
54
65
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
CPU to TCU
15
27
34
41
ns
4.5
Fig.8
tPHL/ tPLH
propagation delay
CPD to TCD
15
27
34
41
ns
4.5
Fig.8
tPHL/ tPLH
propagation delay
PL to Qn
26
46
58
69
ns
4.5
Fig.9
tPHL
propagation delay
MR to Qn
22
40
50
60
ns
4.5
Fig.10
tPHL/ tPLH
propagation delay
Dn to Qn
27
46
58
69
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
PL to TCU, PL to TCD
31
55
69
83
ns
4.5
Fig.12
tPHL/ tPLH
propagation delay
MR to TCU, MR to TCD
29
55
69
83
ns
4.5
Fig.12
tPHL/ tPLH
propagation delay
Dn to TCU,Dn to TCD
32
58
73
87
ns
4.5
Fig.12
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.10
tW
up, down clock pulse width
HIGH or LOW
25
11
31
38
ns
4.5
Fig.7
tW
master reset pulse width
HIGH
20
7
25
30
ns
4.5
Fig.10
tW
parallel load pulse width
LOW
20
8
25
30
ns
4.5
Fig.9
trem
removal time
PL to CPU,CPD
10
2
13
15
ns
4.5
Fig.9
trem
removal time
MR to CPU,CPD
10
0
13
15
ns
4.5
Fig.10
tsu
set-up time
Dn to PL
16
8
20
24
ns
4.5
Fig.11 note:
CPU =CPD =
HIGH
th
hold time
Dn to PL
0
−6
0
0
ns
4.5
Fig.11
th
hold time
CPU to CPD,CPD to CPU
16
7
20
24
ns
4.5
Fig.13
fmax
maximum up, down clock
pulse frequency
20
43
16
13
MHz
4.5
Fig.7


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