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74HCT195 Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74HCT195 Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 9 page December 1990 8 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 AC WAVEFORMS Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for J, K and Dn inputs. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.9 Waveforms showing the set-up and hold times from the parallel enable input (PE) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. |
Podobny numer części - 74HCT195 |
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Podobny opis - 74HCT195 |
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