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74HCT195 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74HCT195
Szczegółowy opis  4-bit parallel access shift register
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HCT195 Arkusz danych(HTML) 2 Page - NXP Semiconductors

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December 1990
2
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
FEATURES
• Asynchronous master reset
• J, K, (D) inputs to the first stage
• Fully synchronous serial or parallel data transfer
• Shift right and parallel load capability
• Complement output from the last stage
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (Qo→Q1) and parallel load, which are controlled
by the state of the parallel load enable (PE) input. Serial
data enters the first flip-flop (Q0) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q0 → Q1 → Q2 → Q3 following each
LOW-to-HIGH clock transition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “195” appears as four common
clocked D flip-flops when the PE input is LOW.
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D0 to D3) is transferred to the respective
Q0 to Q3 outputs. Shift left operation (Q3 → Q2) can be
achieved by tying the Qn outputs to the Dn-1 inputs and
holding the PE input LOW.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition.
There is no restriction on the activity of the J, K, Dn and
PE inputs for logic operation other than the set-up and
hold time requirements. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1,5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Qn
CL = 15 pF; VCC = 5 V
15
15
ns
fmax
maximum clock frequency
57
57
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
105
105
pF


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