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SN74ABT7819A-30PH Arkusz danych(PDF) 2 Page - Texas Instruments

Numer części SN74ABT7819A-30PH
Szczegółowy opis  512 횞 18 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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SN74ABT7819A-30PH Arkusz danych(HTML) 2 Page - Texas Instruments

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SN74ABT7819A
512
× 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21 22 23 24 25
40
26 27 28 29 30 31 32 33 34 35 36 37 38 39
80 79 78 77 76 75 74 73
71 70 69 68 67 66 65 64 63 62 61
72
PN PACKAGE
(TOP VIEW)
AF/AEA
HFA
IRA
GND
A0
A1
VCC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
AF/AEB
HFB
IRB
GND
B0
B1
VCC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7819A is a high-speed, low-power, BiCMOS, bidirectional, clocked FIFO memory.
Two independent 512
× 18 dual-port SRAM FIFOs (FIFOA, FIFOB) on the chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable
almost-full/almost-empty flag.
The SN74ABT7819A is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by the port-A chip select (CSA) and the port-A write/read select
(W/RA). When both CSA and W/RA are low, the outputs are active. The A0–A17 outputs are in the
high-impedance state when either CSA or W/RA is high. Data is written to FIFOA–B from port A on the
low-to-high transition of the port-A clock (CLKA) input when CSA is low, W/RA is high, the port-A write enable
(WENA) is high, and the port-A input-ready (IRA) flag is high. Data is read from FIFOB–A to the A0–A17 outputs
on the low-to-high transition of CLKA when CSA is low, W/RA is low, the port-A read enable (RENA) is high,
and the port-A output-ready (ORA) flag is high.


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