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74HC564 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74HC564
Szczegółowy opis  Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC564 Arkusz danych(HTML) 2 Page - NXP Semiconductors

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December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
74HC/HCT564
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Qn
CL = 15 pF; VCC =5 V
15
16
ns
fmax
maximum clock frequency
127
62
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
27
27
pF


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