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74HC595BQ Arkusz danych(PDF) 20 Page - NXP Semiconductors |
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74HC595BQ Arkusz danych(HTML) 20 Page - NXP Semiconductors |
20 / 28 page 2003 Jun 25 20 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth MLB196 th tsu th tsu Q7' output SH_CP input DS input VM VM VM Fig.9 Waveforms showing the data set-up and hold times for the DS input. 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth MLB197 tPHL tW VM VM VM SH_CP input trem MR input Q7' output Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SH_CP) removal time. 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. |
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