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ADSP-2187NKST-320 Arkusz danych(PDF) 9 Page - Analog Devices |
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ADSP-2187NKST-320 Arkusz danych(HTML) 9 Page - Analog Devices |
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9 / 45 page  –9– REV. 0 ADSP-218xN Series •The RESET pin also can be used to terminate power- down. • Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xN is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA, and auto- buffer cycle steals still occur. Slow Idle The IDLE instruction is enhanced on ADSP-218xN series members to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: IDLE (N); where N = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the in- struction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, ADSP-218xN series members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE Figure 1 shows typical basic system configurations with the ADSP-218xN series, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode-selectable). Programmable wait state gen- eration allows the processor to connect easily to slow periph- eral devices. ADSP-218xN series members also provide four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hard- ware, additional system peripherals can be added in this mode to generate and latch address signals. Figure 1. Basic System Interface In ser t s yst em int erf ac e d iag ram he re 1/2X CLOCK OR CRYSTAL FL0–2 CLKIN XTAL SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 SERIAL DEVICE A0–A21 DATA BYTE MEMORY I/O SPACE (PERIPHERALS) DATA ADDR DATA ADDR 2048 LOCATIONS OVERLAY MEMORY TWO 8K PM SEGMENTS D23–0 A13–0 D23–8 A10–0 D15–8 D23–16 A13–0 14 24 SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 DATA23–0 ADSP-218xN CS CS 1/2X CLOCK OR CRYSTAL CLKIN XTAL FL0–2 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 16 IDMA PORT IRD/D6 I WR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 1 16 A0 DATA23–8 IOMS BMS DMS CMS BR BG BGH PWD PWDACK HOST MEMORY MODE FULL MEMORY MODE MODE D/PF3 MODE C/PF2 MODE B/PF1 MODE A/PF0 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 I RQL1/PF6 MODE D/PF3 MODE C/PF2 MODE B/PF1 MODE A/PF0 WR RD SYSTEM INTERFACE OR µCONTROLLER IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 IOMS BMS PMS CMS BR BG BGH PWD PWDACK WR RD ADSP-218xN DMS TWO 8K DM SEGMENTS PMS ADDR13–0 |
Podobny numer części - ADSP-2187NKST-320 |
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Podobny opis - ADSP-2187NKST-320 |
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