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54ABT543 Arkusz danych(PDF) 2 Page - National Semiconductor (TI) |
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54ABT543 Arkusz danych(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Pin Descriptions Pin Names Description OEAB , OEBA Output Enable Inputs LEAB , LEBA Latch Enable Inputs CEAB , CEBA Chip Enable Inputs A 0–A7 Side A Inputs or TRI-STATE Outputs B 0–B7 Side B Inputs or TRI-STATE Outputs Functional Description The ’ABT543 contains two sets of D-type latches, with sepa- rate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB ) input must be low in order to enter data from the A port or take data from the B port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB ) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA , LEBA and OEBA . Data I/O Control Table Inputs Latch Status Output Buffers CEAB LEAB OEAB H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = High Voltage Level L = Low Voltage Level X = Immaterial Logic Diagram 10021803 www.national.com 2 |
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