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ADT7302ARTZ-REEL7 Arkusz danych(PDF) 4 Page - Analog Devices |
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ADT7302ARTZ-REEL7 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 14 page ADT7302 Preliminary Technical Data Rev. PrE | Page 4 of 14 TIMING CHARACTERISTICS Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 3. TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted. Table 2. Parameter Limit Unit Comments t1 5 ns min CS to SCLK Setup Time t2 25 ns min SCLK High Pulse Width t3 25 ns min SCLK Low Pulse Width t4 1 35 ns max Data Access Time after SCLK Falling Edge t5 20 ns min Data Setup Time prior to SCLK Rising Edge t6 5 ns min Data Hold Time after SCLK Rising Edge t7 5 ns min CS to SCLK Hold Time t81 40 ns max CS to DOUT High Impedance 1 Measured with the load circuit of Figure 2. 1.6V 200 µA 200 µAIOH IOL TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time |
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