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ADM1064ASU Arkusz danych(PDF) 6 Page - Analog Devices

Numer części ADM1064ASU
Szczegółowy opis  Super Sequencer with Voltage Readback ADC
Download  32 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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ADM1064ASU Arkusz danych(HTML) 6 Page - Analog Devices

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ADM1064
Rev. 0 | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SERIAL BUS TIMING
Clock Frequency, fSCLK
400
kHz
Bus Free Time, tBUF
4.7
µs
Start Setup Time, tSU;STA
4.7
µs
Start Hold Time, tHD;STA
4
µs
SCL Low Time, tLOW
4.7
µs
SCL High Time, tHIGH
4
µs
SCL, SDA Rise Time, tr
1000
µs
SCL, SDA Fall Time, tf
300
µs
Data Setup Time, tSU;DAT
250
ns
Data Hold Time, tHD;DAT
5
ns
Input Low Current, IIL
1
µA
VIN = 0
SEQUENCING ENGINE TIMING
State Change Time
10
µs
1 At least one of the VH, VP1-4 pins must be
≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested, but is supported by characterization data at initial product release.


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