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74ACT533PC Arkusz danych(PDF) 1 Page - Fairchild Semiconductor |
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74ACT533PC Arkusz danych(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2005 Fairchild Semiconductor Corporation DS500311 www.fairchildsemi.com August 1999 Revised March 2005 74ACT533 Octal Transparent Latch with 3-STATE Outputs General Description The ACT533 consists of eight latches with 3-STATE out- puts for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Inverted version of the ACT373 s TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions FACT ¥ is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74ACT533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT533MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs |
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Podobny opis - 74ACT533PC |
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