MC74AC648 MC74ACT648

5-2

FACT DATA

FUNCTION TABLE

Inputs

Data I/O*

Operation or Function

G

DIR

CAB

CBA

SAB

SBA

A0–A7

B0–B7

Operation or Function

H

H

X

X

H or L

H or L

X

X

X

X

Input

Input

Isolation

Store A and B Data

L

L

L

L

X

X

X

X

X

X

L

H

Output

Input

Real Time B Data to A Bus

Stored B Data to A Bus

L

L

H

H

X

H or L

X

X

L

H

X

X

Input

Output

Real Time A Data to B Bus

Stored A Data to B Bus

* The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus

pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

1 OF 8 CHANNELS

D0

C0

D0

C0

CAB

SAB

DIR

CBA

SBA

G

B0

A0

TO 7 OTHER CHANNELS

LOGIC DIAGRAM

Please note that this diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation delays.

1

CAB

2

SAB

3

DIR

4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

12

GND

24

23

22

21

20

19

18

17

16

14

13

VCC

CBA

SBA

G

B0

B1

B2

B3

B4

B5

B6

B7

PIN NAMES

A0–A7

Data Register Inputs

Data Register A Outputs

B0–B7

Data Register B Inputs

Data Register B Outputs

CAB, CBA

Clock Pulse Inputs

SAB, SBA

Transmit/Receive Inputs

DIR, G

Output Enable Inputs

15