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MC74F161A Arkusz danych(PDF) 2 Page - Motorola, Inc |
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MC74F161A Arkusz danych(HTML) 2 Page - Motorola, Inc |
2 / 4 page 4-76 FAST AND LS TTL DATA MC74F161A • MC74F163A CP D NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. LOGIC DIAGRAM DETAIL A DETAIL A DETAIL A DETAIL A P0 P1 P3 P2 CEP CET CP Q0 Q1 Q2 Q3 MR (MC74F161A) SR (MC74F163A) Q0 Q0 TC CP CP D Q Q CD MC74F161A MC74F163A MC74F163A ONLY MC74F161A ONLY PE FUNCTIONAL DESCRIPTION The MC74F161A and MC74F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q out- puts (except due to Master Reset of the MC74F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transi- tion of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous re- set (MC74F161A), synchronous reset (MC74F163A), parallel load, count-up and hold. Five control inputs Master Reset (MR, MC74F161A), Synchronous Reset (SR, MC74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — determine the mode of operation, as shown in the Function Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows infor- mation on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (MC74F161A) or SR (MC74F163A) HIGH, CEP and CET per- mit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74F161A and MC74F163A use D-type edge-trig- gered flip-flops and changing the SR, PE, CEP, and CET in- puts when the CP is in either state does not cause errors, pro- vided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. |
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