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ADAU1701JSTZ-RL Arkusz danych(PDF) 6 Page - Analog Devices |
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ADAU1701JSTZ-RL Arkusz danych(HTML) 6 Page - Analog Devices |
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6 / 43 page  ADAU1701 Preliminary Technical Data Rev. PrF | Page 6 of 43 tSIS SDATA_INx Setup To BCLK_IN rising 10 ns tSIH SDATA_INx Hold From BCLK_IN rising 10 ns tLOS OUTPUT_LRCLK Setup Slave mode 10 ns tLOH OUTPUT_LRCLK Hold Slave mode 10 ns tTS OUTPUT_BCLK Falling to OUTPUT_LRCLK Timing Skew ns tSODS SDATA_OUTx Delay Slave mode, from OUTPUT_BCLK falling 40 ns tSODM SDATA_OUTx Delay Master mode, from OUTPUT_BCLK falling 40 ns SPI PORT tCCPL CCLK Pulse Width LO TBD ns tCCPH CCLK Pulse Width HI TBD ns tCLS CLATCH Setup To CCLK rising TBD ns tCLH CLATCH Hold From CCLK rising TBD ns tCLPH CLATCH Pulse Width HI TBD ns tCDS CDATA Setup To CCLK rising TBD ns tCDH CDATA Hold From CCLK rising TBD ns tCOD COUT Delay From CCLK rising TBD ns I2C PORT fSCL SCL Clock Frequency 400 kHz tSCLH SCL High 0.6 μs tSCLL SCL Low 1.3 μs tSCS Setup Time Relevant for Repeated Start Condition 0.6 μs tSCH Hold Time After this period the 1st clock is generated 0.6 μs tDS Data Setup Time 100 ns tSCR SCL Rise Time 300 ns tSCF SCL Fall Time 300 ns tSDR SDA Rise Time 300 ns tSDF SDA Fall Time 300 ns tBFT Bus-Free Time Between Stop and Start 0.6 MULTIPURPOSE PINS & RESET tGRT GPIO Rise Time TBD ns tGFT GPIO Fall Time TBD ns tGIL GPIO Input Latency Until high/low value read by core 1.5 × 1/fs μs tRLPW RESETB LO Pulse Width 20 ns 1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 45. PLL Table 7. Parameter Min Typ Max Unit Operating Range TBD TBD MHz Lock Time 20 ms REGULATOR1 Table 8. Parameter Min Typ Max Unit DVDD Voltage 1.8 V 1 Regulator specifications are calculated using an FZT953 transistor in the circuit. |
Podobny numer części - ADAU1701JSTZ-RL |
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Podobny opis - ADAU1701JSTZ-RL |
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