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ADAU1701JSTZ-RL Arkusz danych(PDF) 11 Page - Analog Devices |
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ADAU1701JSTZ-RL Arkusz danych(HTML) 11 Page - Analog Devices |
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11 / 43 page  Preliminary Technical Data ADAU1701 Rev. PrF | Page 11 of 43 DGND with a 100 nF capacitor. 14 D_IO MP7 Multi-Purpose – GPIO or Serial output port data 1 (SDATA_OUT1) 15 D_IO MP6 Multi-Purpose – GPIO, Serial output port data 0, or TDM data output (SDATA_OUT0) 16 D_IO MP10 Multi-Purpose – GPIO or Serial output port LRCLK (OUTPUT_LRCLK) 17 A_OUT VDRIVE Drive for 1.8 V regulator. The base of the voltage regulator’s external PNP transistor is driven from VDRIVE. 18 PWR IOVDD Input and Output pins supply. The voltage on this pin sets the highest input voltage that should be seen on the digital input pins. This pin is also the supply for the digital output signals on the control port and MP pins. IOVDD should always be set to 3.3 V. The current draw of this pin is variable because it is dependant on the loads of the digital outputs. 19 D_IO MP11 Multi-Purpose – GPIO or Serial output port BCLK (OUTPUT_BCLK) 20 D_IN ADDR1/CDATA/WB ADDR1: I2C Address 1, in combination with ADDR0 it will set the I2C address of the IC. Four ADAU1701s to be used on the same I2C bus. CDATA: SPI Data Input WB: EEPROM Writeback trigger. A rising (default) or falling (if set in the EEPROM messages) edge on this pin will trigger a write-back of the interface registers to the external EEPROM. This function can be used to save parameter data on power-down. 21 D_IN CLATCH / WP CLATCH: This SPI latch signal must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. WP: Self-boot EEPROM write protect. This pin is an open collector output when in selfboot mode. The ADAU1701 will pull this low to prohibit writes to an external EEPROM. This pin should be pulled high to 3.3 V. 22 D_IO SDA/COUT SDA: This I2C data pin is a bidirectional open collector. The line connected to this pin should have a 2.2 kΩ pull-up resistor. COUT: This SPI data output is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. 23 D_IO SCL/CCLK SCL: This I2C clock pin is always an open collector input when in I2C control mode. In self-boot mode this pin will be an open collector output (I2C master). The line connected to this pin should have a 2.2 kΩ pull-up resistor. CCLK: This SPI clock may either run continuously or be gated off in between SPI transactions. 24 PWR DVDD 1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND with a 100 nF capacitor. 25 PWR DGND DGND is a digital ground pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. dGND should be decoupled to a DVDD pin with a 100 nF capacitor. 26 D/A_IO MP9 Multi-Purpose – GPIO, serial output port data 3 (SDATA_OUT3), or auxiliary ADC input 0 27 D/A_IO MP8 Multi-Purpose – GPIO, serial output port data 2 (SDATA_OUT2), or auxiliary ADC input 3 28 D/A_IO MP3 Multi-Purpose – GPIO, serial input port data 3 (SDATA_IN3), or auxiliary ADC input 2 29 D/A_IO MP2 Multi-Purpose – GPIO, serial input port data 2 (SDATA_IN2), or auxiliary ADC input 1 30 X RSVD Reserved, tie to ground, either directly or through a pull-down resistor. 31 D_OUT OSCO OSCO is the output of the crystal oscillator circuit. A 100 Ω damping resistor should be connected between this pin and the crystal. This output should not be used to directly drive a clock to another IC. If the crystal oscillator is not used, this pin can be left unconnected. 32 D_IN MCLKI MCLKI can either be connected to a 3.3 V clock signal or can be the input from the crystal oscillator circuit. 33 PWR PGND PGND is the PLL ground pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. PGND should be decoupled to |
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Podobny opis - ADAU1701JSTZ-RL |
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