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LM3743 Arkusz danych(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Numer części LM3743
Szczegółowy opis  N-Channel FET Synchronous Buck Controller for Low Output Voltages
Download  23 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM3743 Arkusz danych(HTML) 2 Page - National Semiconductor (TI)

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Connection Diagram
20177402
10-Lead Plastic MSOP
NS Package Number MUB10A
Top View
Ordering Information
Order Number
Frequency Option
Top Mark
NSC Package Drawing
Supplied As
LM3743MM-300
300 kHz
SKPB
MUB10A
1000 units in Tape and Reel
LM3743MMX-300
300 kHz
SKPB
MUB10A
3500 units in Tape and Reel
LM3743MM-1000
1 MHz
SKNB
MUB10A
1000 units in Tape and Reel
LM3743MMX-1000
1 MHz
SKNB
MUB10A
3500 units in Tape and Reel
Pin Descriptions
VCC (Pin 1) Supply rail for the controller section of the IC. A
minimum capacitance of 1 µF, preferably a multi-layer ce-
ramic capacitor type (MLCC), must be connected as close
as possible to the V
CC and GND pin anda1to 4.99
resistance must be connected in series from the supply rail
to the Vcc pin. See VCC FILTERING in the Design Consid-
eration section for further details.
LGATE (Pin 2) Gate drive for the low-side N-channel MOS-
FET. This signal is interlocked with HGATE to avoid a shoot-
through problem.
GND (Pin 3) Power ground (PGND) and signal ground
(SGND). Connect the bottom feedback resistor between this
pin and the feedback pin.
ILIM (Pin 4) Low side current limit threshold setting pin. This
pin sources a fixed 50 µA current. A resistor of appropriate
value should be connected between this pin and the drain of
the low-side N-FET.
FB (Pin 5) Feedback pin. This is the inverting input of the
error amplifier used for sensing the output voltage and com-
pensating the control loop.
COMP/EN (Pin 6) Output of the error amplifier and enable
pin. The voltage level on this pin is compared with an inter-
nally generated ramp signal to determine the duty cycle. This
pin is necessary for compensating the control loop. Forcing
this pin to ground will shut down the IC.
SS/TRACK (Pin 7) Soft-start and tracking pin. This pin is
connected to the non-inverting input of the error amplifier
during initial soft-start, or any time the voltage is below the
reference. To track the rising ramp of another power supply’s
output, connect a resistor divider from the output of that
supply to this pin as described in Application Information.
SW (Pin 8) Switch pin. The lower rail of the high-side N-FET
driver. Also used for the high side current limit sensing.
HGATE (Pin 9) Gate drive for the high-side N-channel MOS-
FET. This signal is interlocked with LGATE to avoid a shoot-
through problem.
BOOT (Pin 10) Supply rail for the N-channel MOSFET high
gate drive. The voltage should be at least one gate threshold
above the regulator input voltage to properly turn on the
high-side N-FET. See MOSFET Gate Drivers in the Applica-
tion Information section for more details on how to select
MOSFETs.
www.national.com
2


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