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ADF4002BRUZ-RL7 Arkusz danych(PDF) 11 Page - Analog Devices |
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ADF4002BRUZ-RL7 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 24 page ADF4002 Rev. 0 | Page 11 of 24 REFERENCE COUNTER LATCH MAP LDP 0 1 ABP2 ABP1 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns R14 R13 R12 .......... R3 R2 R1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 X = DON’T CARE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 (0) C1 (0) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 ABP1 ABP2 T1 T2 LDP DB21 DB22 DB23 00 X RESERVED TEST MODE BITS ANTI- BACKLASH WIDTH 14-BIT REFERENCE COUNTER CONTROL BITS DIVIDE RATIO ANTIBACKLASH PULSEWIDTH TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION. OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 17. Reference Counter Latch Map |
Podobny numer części - ADF4002BRUZ-RL7 |
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Podobny opis - ADF4002BRUZ-RL7 |
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