ADG3123

Rev. A | Page 9 of 12

TERMINOLOGY

Logic input high voltage at Pin A1 to Pin A8.

Logic input low voltage at Pin A1 to Pin A8.

Leakage current at Pin A1 to Pin A8.

Capacitance measured at Pin A1 to Pin A8.

Logic output high voltage at Pin Y1 to Pin Y8.

Logic output low voltage at Pin Y1 to Pin Y8.

Ro

Output impedance.

Propagation delay through the part measured between the input

signal applied to any one channel and its corresponding output

for a low-to-high transition (see Figure 2).

Propagation delay through the part measured between the input

signal applied to any one channel and its corresponding output

for a high-to-low transition (see Figure 2).

Rise time of the output signal at Pin Y1 to Pin Y8 (see Figure 2).

Fall time of the output signal at the Pin Y1 to Pin Y8

(see Figure 2).

Frequency of the signal applied to the A1 to A8 input pins.

Input voltage used to generate the high logic levels for Y1 to Y6

outputs.

Positive power supply voltage. Also used to generate the high

logic levels for Y7 to Y8 outputs.

Negative power supply voltage. It is used to generate the low

logic level for Y1 to Y8 outputs.

GND

Ground (0 V) reference.