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ADS8328IPW Arkusz danych(PDF) 7 Page - Burr-Brown (TI) |
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ADS8328IPW Arkusz danych(HTML) 7 Page - Burr-Brown (TI) |
7 / 40 page www.ti.com TIMING CHARACTERISTICS ADS8327 ADS8328 SLAS415A – APRIL 2006 – REVISED MAY 2006 All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (1)(2) PARAMETER MIN TYP MAX UNIT External, 0.5 10.5 fCCLK = 1/2 fSCLK fCCLK Frequency, conversion clock, CCLK MHz Internal 10.5 12 12.2 tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tc(SCLK) tsu(CSF-SCLK1R) Setup time, falling edge of CS to SCLK 5 ns - 5 tc(SCLK) twL(SCLK) Pulse duration, SCLK low 8 ns - 8 tc(SCLK) twH(SCLK) Pulse duration, SCLK high 8 ns - 8 I/O Clock only 30 I/O and conversion clock 47.6 1000 tc(SCLK) Cycle time, SCLK ns I/O Clock, chain mode 30 I/O and conversion clock, 47.6 1000 chain mode Delay time, falling edge of SCLK to SDO td(SCLKF-SDOINVALID) 10-pF Load 8 ns invalid Delay time, falling edge of SCLK to SDO td(SCLKF-SDOVALID) 10-pF Load 25 ns valid Delay time, falling edge of CS to SDO valid, td(CSF-SDOVALID) 10-pF Load 25 ns SDO MSB output tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO td(CSR-SDOZ) 5 ns 3-state Setup time, last falling edge of SCLK before tsu(lastSCLKF-CSR) 10 ns rising edge of CS/FS Delay time, CDI high to SDO high in daisy td(SDO-CDI) 10-pF Load, chain mode 25 ns chain mode (1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. 7 Submit Documentation Feedback |
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